Pat Gelsinger to Rapidus: “Leap ahead, don’t just catch up”
Former Intel chief executive Pat Gelsinger has thrown down the gauntlet to Japan’s fledgling foundry Rapidus, warning that chasing Taiwan Semiconductor Manufacturing Co. (TSMC) with “me-too” technology will not be enough as the start-up races to launch 2-nanometre production in 2027.
A friendly, but pointed, challenge
Speaking to reporters in Tokyo, Gelsinger applauded Japan’s push to restore domestic chip manufacturing but said Rapidus must deliver “fundamental differentiating technologies” if it hopes to win leading-edge customers away from TSMC. His comments underline industry scepticism that scale alone can level the playing field against the world’s largest contract chipmaker.
Rapidus’ answer: one-stop fab-and-package
Rapidus, created in 2022 with backing from eight Japanese conglomerates and heavy government subsidies, believes its ace card is an integrated site in Chitose, Hokkaido that combines front-end wafer fabrication with fully automated advanced-packaging lines. By keeping 3-D stacking, redistribution-layer and chiplet assembly under the same roof, the company says it can slash cycle times for customised AI and high-performance-computing parts. The packaging lines, however, will not switch on until after the initial wafer pilot phase.
Pilot production imminent
Construction of the Innovative Integration for Manufacturing (IIM-1) fab is on schedule, with ASML’s most advanced NXE:3800E extreme-ultraviolet scanner and supporting deep-ultraviolet tools already installed. A ceremonial “first light” is expected in the coming weeks as engineers begin printing gate-all-around transistors on 300 mm wafers ahead of sample deliveries promised by July.
Building the packaging brain trust
Next door, Rapidus Chiplet Solutions (RCS) is taking shape inside Seiko Epson’s campus. The 9,000 m² cleanroom will house pilot lines for flip-chip BGA, silicon interposers, hybrid bonding and high-bandwidth-memory modules. Tool installation starts this month, with R&D slated to ramp in 2026 under a Japanese government programme to master chiplet and 3-D integration for the 2 nm era.
Government money keeps flowing
Tokyo is backing the gamble with fresh capital. The fiscal-2025 budget sets aside at least ¥100 billion (about US $635 million) in additional equity for Rapidus, on top of earlier subsidies totalling almost ¥1 trillion. Officials say the cash is designed to crowd-in private investment and ensure the facility reaches high-volume output by 2027.
The competitive hill to climb
Even with deep pockets and IBM as a process-development partner, analysts note that Rapidus will debut its “2 nm-class” node roughly a year after TSMC’s N2 ramps and in the same window as Samsung’s SF2 and Intel’s 18A offerings. Winning marquee customers will hinge on yield, cost — and the “leap-ahead capabilities” Gelsinger says are essential.
The road to 2027
For now, Rapidus must execute flawlessly: prove pilot yields, stand-up its packaging lines and lock in a commercial pipeline. If Gelsinger’s advice resonates, the company’s differentiator may be more than an accelerated workflow; it could be a new template for building complex AI systems locally, from wafer to finished package, in a single Japanese hub.